Aberrations in manufacturing processes of integrated circuits may result in various types of abnormalities in the circuit performance. Certain aberrations can result in functional failures of the design. However, certain other aberrations may result in circuits that, while free from functional failures, operate at a frequency that is slower than that expected for the design.
These aberrations in performance may result from logic gates containing variations in their device parameters or from various other causes. Parametric variations include variations in channel length and effective width. These variations, in turn, cause variations in the logic path delays. Variations in logic path delays are becoming relatively larger as manufacturing processes, and thus feature sizes, decrease. This variation in logic path delays is bringing about difficulty in converging chip timing and in meeting the desired operating frequency. Further, due to minimum delay violations, functional failures may eventually ensue.
Various methods have been devised to detect when performance-based variations may affect a circuit. For example, “at-speed” Automated Test Pattern Generation (ATPG) can be utilized to determine when critical paths in a circuit have maximum operating frequencies that do not meet operating frequencies specified for the circuit. However, such tests only provide an indication of a problem, these tests do not aid in identifying the gate (or gates) associated with the problem. Other methods have been devised for attempting to narrow the location of gates that have aberrant timing. However, these methods have largely produced procedures for general area identification.